1. Field of the Invention
The present invention relates to a semiconductor memory device and a programming and erasing method of a memory cell, and more particularly, to a programming and erasing method which can effectively used for a nonvolatile semiconductor memory device using a variable resistive element.
2. Description of the Related Art
As an EEPROM which is a conventional electrically erasable and programmable read-only memory, a NAND cell type EEPROM which can increase the packing density is known. Japanese Unexamined Patent Publication No.H5-182474 describes as follows. In the NAND cell type EEPROM, a plurality of memory cells are connected to each other in series and connected to a bit line as one unit such that the plurality of memory cells use sources and drains of the adjacent memory cells. The memory cell is usually of an FETMOS structure in which a charge-storage layer and a control gate are laminated on each other. A memory cell array is packed in a positive type well (P type well) formed on a positive type substrate (P-type substrate) or a negative type substrate (N type substrate). A drain of the NAND cell is connected to a bit line through a selection gate, and a source side of the NAND cell is connected to a source line (reference potential line) through the selection gate. The control gate of the memory cell is continuously disposed in a line direction and becomes a word line.
The NAND cell type EEPROM operates as follows. The programming operation of data is carried out from a memory cell located furthest from the bit line in this order. High voltage Vpp (about 20V) is applied to a control gate of the selected memory cell, intermediate potential VppM (about 10V) is applied to a selection gate and a control gate of a memory cell located closer to the bit line than the former memory cell, and 0V or intermediate potential is applied to the bit line in accordance with data. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electron injection is generated in the floating gate from the substrate. With this, a threshold voltage of the selected memory cell is shifted in the normal direction. This state is defined as “1” for example. When intermediate potential is applied to the bit line, electron injection is not caused, the threshold voltage is not varied and stops in negative. This state is “0”.
Data erasion is simultaneously carried out with respect to all the memory cells in the NAND cell. That is, all the control gates are set to 0V, high voltage of 20V is applied to the selection gate, the bit line, the source line, the P type well in which the memory cell array is formed, and the N type substrate. With this, electrons of the floating gates in all the memory cells are discharged toward the substrate side, and the threshold voltage is shifted in the negative direction.
Data reading operation is carried out in such a manner that voltage of the control gate of the selected memory cell is set to 0V, the control gates and selection gates of other memory cells is set to source potential Vcc (=5V), and it is detected whether current flows through the selected memory cell.
As apparent from the above explanation of the operation, in the NAND cell type EEPROM, the non-selected memory cells function as transfer gates at the time of programming and reading operation. In view of this point, constraints are added to threshold voltage of a programmed memory cell. For example, a preferable range of the threshold voltage of a memory cell which is programmed with “1” is about 0.5 to 3.5V. If variation with time after data programming, variation in producing parameter of memory cell and variation of source potential are taken into consideration, it is required that distribution of threshold voltage after data programming is smaller than the preferable range.
However, in the case of the conventional method in which the programming potential and programming time are fixed, and all the memory cells are programmed with data under the same condition, it is difficult to contain the threshold voltage range after the programming of “1” in a tolerance. For example, characteristics of memory cell are varied due to variation of producing process thereof. Therefore, if the programming characteristics are considered, there are memory cells which can easily be programmed and memory cells which are difficult to be programmed. Conventionally, all the memory cells are programmed under the same condition with sufficient lead time to perform the programming so that the memory cell which is difficult to be programmed can sufficiently be programmed. With this method, however, the memory cell which is easily programmed is programmed more than necessary, and the threshold voltage exceeds the tolerance.
On the other hand, if threshold voltage of a memory cell programmed with “0” or of a NAND cell from which data is erased becomes greater by certain value in the negative direction, this is also a problem. In the threshold voltage of the memory cell programmed with “0”, cell current (reading current) at the time when data is read is varied due to this problem and as a result, access time is varied. Thus, specification of the EEPROM is varied. If data is not erased by data erasion, threshold voltage in the state “1” is increased more than necessary due to subsequent data programming, and the threshold voltage exceeds its tolerance.
To solve these problems, the above publication proposes a NAND cell type EEPROM having a programming verify function. Here, this EEPROM has a programming verify control circuit including a function to apply first programming verify potential in succession to control gates of memory cells in the NAND cell which is selected at the time of data programming, and for reading data to confirm a programming shortage state, and a function for applying second programming verify potential to the control gate of the selected memory cell, and for reading data to confirm an excessively programmed state. With this, if there is a memory cell which is lacking in programming, the programming operation is added, and first data programming verify potential is applied to the memory cell to confirm the programmed state again. This operation is repeated, and after the first programming verify and data re-programming with respect to the memory cell are completed, the confirmation operation of the excessively programmed state using the second programming verify potential is carried out. By repeating such operation, a memory cell having required threshold voltage is controlled such that the memory cell is not programmed again, thereby solving the above problem.
U.S. Pat. No. 5,287,317 proposes a similar electrically erasable and programmable semiconductor memory. That is, in the case of data programming, as shown in FIG. 14, after a programming command is input (step S1) in the electrically erasable and programmable semiconductor memory, if address and data are input (step S2), application of program pulse to a selected memory cell is started, and data is programmed in the memory cell (step S3). After the application of program pulse is stopped, if a program verify command is input, the memory is brought into a program verify mode (step S4), and reading operation of data from the programmed memory cell is started (step S5). The data is read, and the read data and an initially inputted expected value (reference) data are compared with each other (step S6). If they coincide with each other, the program is normally completed, the memory is brought into a reading mode, and the program is completed. If they do not coincide with each other, the program pulse is again applied (step S7). This series of operation is repeated until all data coincides with each other. FIG. 15 is a timing chart showing that after the program pulse is applied, a series of operation for carrying out the verify operation is executed, and since the expected value data and programmed data coincide with each other through three trials, the program is completed.
As described above, in the electrically erasable and programmable semiconductor memory (EEPROM), the program pulse is applied until the expected value data and programmed data coincide with each other and then, the series of operation in which the verify operation is carried out is repeated, thereby setting a threshold voltage of a memory cell to a desired value.
The above technique can also be employed for a memory using an RRAM (Novel resistance control nonvolatile RAM) which is a nonvolatile variable resistive element which becomes a focus of attention.
If the conventional program verify function is employed, as compared with an EEPROM not having the program verify function, it is possible to reduce the variation in threshold value. However, while the program pulse is applied, the programming operation is forcibly carried out. Therefore, there is an adverse possibility that the threshold value of the memory cell largely exceeds a desired value during application. The characteristics of the memory cell are varied due to variation of producing process thereof as described above. Therefore, if the programming characteristics are considered, there are memory cells which can easily be programmed and memory cells which are difficult to be programmed. Thus, it is difficult to optimally and uniformly set the application time. A semiconductor memory using a nonvolatile variable resistive element such as an RRAM has the same problem, and it is difficult to set a resistant value to a desired value. Especially in a semiconductor memory such as the RRAM, when multilevel technique for storing a state of one of a plurality of resistant states in one memory cell is employed, it is necessary to set the resistant value having small variation. In the above conventional technique, however, it is difficult to precisely set the resistant value. There is also a problem that after the program pulse is applied, since the series of verify operation must be repeated, the programming time becomes long.